Due to several reasons there is only a small time margin for a digital logic to work at a receiver of a communications system. The timing margin gets worse when data rate rises higher. The timing margin may be reduced by several imperfections, such as transmitter jitter and skew, clock duty cycle in transmitter clock, printed board trace length differences (causes static skew), receiver asymmetries (bias current mismatches, offset-voltages etc.), and delays in internal clock path.
In systems where two signals are used to transmit data, the skew between the two signals can cause instability in the output signals. The signals used may be data and strobe or data and clock depending on the operation mode. When there is skew between two signals the internal clock of the receiver may get asymmetric, that is, the duty cycle deviates from 50%. FIG. 1 illustrates an ideal case where skew between data and strobe signals is zero. In this case the skew is calculated as deviations from the ideal locations of the signal edges. CLK_XOR 14 is a slightly delayed XOR function of DATA 10 and STROBE 12, and it shows 50% duty cycle. FIG. 2 illustrates a non-ideal case where STROBE 12 rising edge has moved from an ideal position 13 closer to the DATA rising edge. Thus, the skew is not zero. Now the pulse shape of the CLK_XOR 14 is not symmetric any more, i.e. the duty cycle is different from 50%. If the pulse shape gets too much distorted, the setup or hold-times of internal flip-flops may get violated and the data is captured incorrectly.